High-Speed PCBs and DDR5 Memory Technology Exploration with Stephen Slater
In the rapidly evolving world of technology, a significant milestone has been reached with the advent of DDR5. This new memory standard, offering speeds above 5200 MT/s per pin, presents unique challenges in terms of signal integrity, particularly crosstalk in PCB layouts.
Keysight Technologies, a leading name in electronic design and test solutions, is at the forefront of this revolution. Stephen Slater, a product manager in High-Speed Digital Simulation Technology at Keysight, shares his expertise in high-speed SerDes channel simulations, DDR simulations, and electromagnetic simulations for PCB applications.
One of the key focuses for Keysight is to simplify the design process for DDR5, particularly in reducing crosstalk. Here are the critical considerations for achieving this:
- Controlled impedance with careful trace width and spacing: Design trace widths and spacing to support controlled impedance, typically following copper thickness-based spacing rules (e.g., ≥8 mil for 2 oz copper).
- Minimize stub lengths and remove unconnected traces: Stubbed or unconnected traces on signal nets, especially differential pairs, can cause reflections and crosstalk.
- Continuous, uninterrupted ground planes below signal layers: DDR5 signals require continuous ground reference planes to provide dedicated return paths.
- Ground vias adjacent to signal vias: Adding ground vias near signal vias during layer transitions helps maintain a tight return path for signals.
- Multi-layer PCB designs (e.g., 16 layers): Using more layers allows splitting signals and ground/power planes, significantly improving signal routing.
- Keep differential pairs tightly coupled and separated from other pairs: Maintain pair symmetry and proper spacing from other pairs.
- Avoid routing memory signals across splits or gaps in reference planes: Discontinuities in ground or power planes under signals cause undesired inductance and coupling.
- Use of stitching capacitors and ground fills when appropriate to further suppress crosstalk and electromagnetic interference (EMI).
These considerations are crucial in maintaining signal integrity at DDR5 speeds, where crosstalk and reflection losses become critical concerns due to high-frequency operation and tight spacing constraints in PCB layouts.
Moreover, the shift from DDR4 to DDR5 is a significant redesign that requires careful consideration, particularly in terms of signal integrity. Keysight has created a library of PCI express-gen-5 reference channels for system simulations, and their advanced design system, Pathwave ADS, serves as their primary flagship product, offering various useful tools.
The High-Speed PCB Design Guide, another valuable resource from Keysight, includes explanations of signal integrity issues, understanding transmission lines and controlled impedance, high-speed PCB material selection, and high-speed layout guidelines.
As the industry prepares for an influx of DDR5 designs this year, Keysight's tools and resources are set to play a pivotal role in ensuring the successful implementation of this new standard.
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- To address the crosstalk challenges in DDR5 PCB design, adherence to a controlled impedance, carefully managing trace width and spacing, is crucial. (controlled impedance)
- In the home-and-garden of technology, amidst advancements in data-and-cloud-computing, lifestyle changes are evident in the shift from DDR4 to DDR5, requiring careful management and attention to signal integrity, exemplified by Keysight Technologies' extensive resources and tools. (lifestyle, data-and-cloud-computing, technology)
